Cache Performance !!!

1)  Công thức :
+ CPU time = Instruction count x CPI x Clock cycle time
+ CPI execution =  CPI with idea memory
+ CPI = CPI execution + Mem Stall cycles per instrcution
+ CPU time = Instruction Count x (CPI execution + Mem Stall cycles per instruction ) x Clock cycle time
+ Mem Stall cycles per instruction = Mem accesses per instruction x Miss rate x Miss penalty
+ CPU time = IC x (CPI execution + Mem accesses per instruction x Miss rate x Miss penalty) x Clock cycle time
+ Misses per instruction = Memory accesses per instruction x Miss rate
+ CPU time = IC x (CPI execution + Misses per instruction x Miss penalty)x Clock cycle time 
2) Ví dụ 1;
 Assume the following execution and cache parameters :
- Cache miss penalty = 50 cycles
- Normal instruction execution CPI ignoring memory stalls = 2.0 cycles
- Miss rate = 2%
-  Average memory references/ Instruction =1.33
Lời giải:
CPU time = IC x [CPI execution + Memory accesses/instruction x Miss rate x Miss penalty ] x Clock cycle time
-> CPU time with cache = IC x (2.0+(1.33 x 2% x 50)) x clock cycle time
= IC x 3.33 x Clock cycle time
-> Lower CPI execution increases the impact of cache miss clock cycles.
Ví dụ 2:
+ Suppose a CPU executes at Clock Rate= 200 MHz (5ns per cycle) with a single level of cache.
+ CPI execution = 1.1
+ Instruction mix: 50% arith/logic, 30%  load/store, 20% control
+ Assume a cache miss rate of 1.5% and a miss penalty of 50 cycles.
CPI=CPI execution + mem stalls per instruction
Mem Stalls per instruction = Mem accesses per instruction x Miss rate x Miss penalty
Mem access per instruction = 1+0.3(load/store) = 1.3.
Mem Stalls per instruction = 1.3x 1.5%.50= 0.975.
CPI=1.1+0.975=2.075
The ideal memory CPU with no misses is 2.075/1.1=1.88 times faster.